/////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineer: Kyle D. Gilsdorf
//
// Create Date: 08:07:29 11/04/2011
// Design Name:
// Module Name: seg_display
// Project Name: Lab #2
// Target Devices:
// Tool versions:
// Description: The 7-Segment LED Display module drives the 4 separate LED
// 7-Segment LED Display devices mounted on the FPGA Board.
//
// Dependencies:
// - my_clock
//
// Revision 0.01 - File Created
// Additional Comments:
// - I have provided the entire alphabet so that you can change this to display
//   other text as well.
/////////////////////////////////////////////////////////////////////////////////

module slowclock
  /*************************************************************************
   * Input/Output Declarations and Parameters                              *
   *************************************************************************/
  (// Global Signals                  // -----------------------------------
   input  wire clk,                   // System Clock
   output wire clk_xxMHz);            //

   parameter MSB = 2;//10; change back after testing 

  /***********************************************************
   * Signal Declaration                                      *
   ***********************************************************/   
   reg [MSB:0] count1 = 0;

  /***********************************************************
   * Combinational Logic                                     *
   ***********************************************************/
   assign clk_xxMHz = count1[MSB];

  /***********************************************************
   * Synchronous Logic                                       *
   ***********************************************************/
   always@(posedge clk)
      count1 <= count1 + 1;
	  
  /***********************************************************
   * Module Instantiation                                    *
   ***********************************************************/	  
endmodule

module seg_display
  /*************************************************************************
   * Input/Output Declarations and Parameters                              *
   *************************************************************************/
  (// Global Signals                  // -----------------------------------
   input wire        clk_50MHz,            // System Clock
   input wire         reset_b,        // Push Button for System Reset.
   // 7-Segment LED Interface         // -----------------------------------
  // input  wire          reg_read,     // Register Select Address is valid
   //input  wire [01:00]  reg_addr,     // Register Select
   
	input [15:0] read_data,
	
	output wire [03:00]  reg_data,     // 4-Bit register Value of currently
                                      // address register (valid it read is
                                      // active)
   // 7-Segment LED Display Interface // -----------------------------------
   output wire         dp_dis,        // Period Display
   output reg  [03:00] dis_control,   // Select which of the 4x7-Segment LED
	                                  // Displays to activate.
   output reg  [06:00] led_dis,      // Select which of the 7 LED's in the
	                                  // 7-Segment LED Display

	//input [7:0] read_data,
	output data_displayed,
	output read_pulse
	
	);      
   ///////////////////////////
   // 7-Segment LED Display //
   //       aaaaaaaa        //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //       ggggggggg       //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //       ddddddddd       //
   ///////////////////////////
   //                   6543210
   //                   gfedcba
   parameter _0_  = 7'b1000000;
   parameter _1_  = 7'b1111001;
   parameter _2_  = 7'b0100100;
   parameter _3_  = 7'b0110000;
   parameter _4_  = 7'b0011001;
   parameter _5_  = 7'b0010010;
   parameter _6_  = 7'b0000010;
   parameter _7_  = 7'b1111000;
   parameter _8_  = 7'b0000000;
   parameter _9_  = 7'b0010000;
   parameter A     = 7'b0001000;
   parameter B     = 7'b0000011;
   parameter C     = 7'b1000110;
   parameter D     = 7'b0100001;
   parameter E     = 7'b0000110;
   parameter F     = 7'b0001110;
   parameter G     = 7'b0010000;
   parameter H     = 7'b0001011;
   parameter I     = 7'b1001111;
   parameter J     = 7'b1100001;
   parameter K     = 7'b0001001;
   parameter L     = 7'b1000111;
   parameter M     = 7'b1101010;
   parameter N     = 7'b0101011;
   parameter O     = 7'b1000000;
   parameter P     = 7'b0001100;
   parameter Q     = 7'b0011000;
   parameter R     = 7'b0101111;
   parameter S     = 7'b0010010;
   parameter T     = 7'b0000111;
   parameter U     = 7'b1000001;
   parameter V     = 7'b1100011;
   parameter W     = 7'b1010101;
   parameter X     = 7'b0001001;
   parameter Y     = 7'b0010001;
   parameter Z     = 7'b0100100;
   parameter empty = 7'b1111111;

  /***********************************************************
   * Signal Declaration                                      *
   ***********************************************************/
   wire clk_xxMHz;
	reg [7:0] led_data;
	reg [7:0] led_data2;
	reg [7:0] led_data3;
	reg [7:0] led_data4;
	reg [27:00] delay_c = 0;
	reg delay_flag = 0;
	reg [12:0] COUNT1 = 0;
	reg [1:0] pop_flag = 0;
	reg [1:0] counter = 1;
	reg zeroflag = 0;
	reg zeroflag2 = 0;
	reg zeroflag3 = 0;
	reg zeroflag4 = 0;

  /***********************************************************
   * Combinational Logic                                     *
   ***********************************************************/
   assign dp_dis = 1'b1; // Disable to dot.
  /***********************************************************
   * Synchronous Logic                                       *
   ***********************************************************/
  
	
		always @(posedge clk_50MHz, negedge reset_b)
		begin
		//if (read_data) begin
	   if (reset_b == 1'b0) begin
         led_data4 <= _0_;
      end
		else if (read_data[15:12] == 4'b0000) begin
         led_data4 <= _0_;
			zeroflag4 = 1;
      end
      else if (read_data[15:12]== 4'b0001) begin
         led_data4 <= _1_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12]  == 4'b0010) begin
         led_data4 <= _2_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12]  == 4'b0011) begin
         led_data4 <= _3_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12]  == 4'b0100) begin
         led_data4 <= _4_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12]  == 4'b0101) begin
         led_data4 <= _5_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12]  == 4'b0110) begin
         led_data4 <= _6_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12] == 4'b0111) begin
         led_data4 <= _7_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12] == 4'b1000) begin
         led_data4 <= _8_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12] == 4'b1001) begin
         led_data4 <= _9_;
			zeroflag4 = 1;
      end
		else if (read_data[15:12] == 4'b1010) begin
         led_data4 <= A;
			zeroflag4 = 1;
      end
		else if (read_data[15:12] == 4'b1011) begin
         led_data4 <= B;
			zeroflag4 = 1;
      end
		else if (read_data[15:12] == 4'b1100) begin
         led_data4 <= C;
			zeroflag4 = 1;
      end
		else if (read_data[15:12]== 4'b1101) begin
         led_data4 <= D;
			zeroflag4 = 1;
		end
		else if (read_data[15:12] == 4'b1110) begin
         led_data4 <= E;
			zeroflag4 = 1;
      end
		else if (read_data[15:12] == 4'b1111)	begin
         led_data4 <= F;
			zeroflag4 = 1;
      end
		else begin
		//end
		end
		$display ("led_data2 = %b", led_data2);
	end
	always @(posedge clk_50MHz, negedge reset_b)
	begin
		if (reset_b == 1'b0) begin
         led_data3 <= _0_;
      end
		else begin
		//if (read_data) begin
			if (read_data[11:8] == 4'b0000) begin
				led_data3 <= _0_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8]== 4'b0001) begin
				led_data3 <= _1_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8]  == 4'b0010) begin
				led_data3 <= _2_;
				zeroflag3 = 1;
			
			end
			else if (read_data[11:8]  == 4'b0011) begin
				led_data3 <= _3_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8]  == 4'b0100) begin
				led_data3 <= _4_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8]  == 4'b0101) begin
				led_data3 <= _5_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8]  == 4'b0110) begin
				led_data3 <= _6_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b0111) begin
				led_data3 <= _7_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1000) begin
				led_data3 <= _8_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1001) begin
				led_data3 <= _9_;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1010) begin
				led_data3 <= A;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1011) begin
				led_data3 <= B;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1100) begin
				led_data3 <= C;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1101) begin
				led_data3 <= D;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1110) begin
				led_data3 <= E;
				zeroflag3 = 1;
				
			end
			else if (read_data[11:8] == 4'b1111) begin
				led_data3 <= F;
				zeroflag3 = 1;
				
			end
			else begin
			end
		end
			$display ("led_data = %b", led_data);
		end
	always @(posedge clk_50MHz, negedge reset_b)
	begin
		if (reset_b == 1'b0) begin
         led_data <= _0_;
      end
		else begin
		//if (read_data) begin
			if (read_data[7:4] == 4'b0000) begin
				led_data <= _0_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4]== 4'b0001) begin
				led_data <= _1_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4]  == 4'b0010) begin
				led_data <= _2_;
				zeroflag = 1;
			
			end
			else if (read_data[7:4]  == 4'b0011) begin
				led_data <= _3_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4]  == 4'b0100) begin
				led_data <= _4_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4]  == 4'b0101) begin
				led_data <= _5_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4]  == 4'b0110) begin
				led_data <= _6_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b0111) begin
				led_data <= _7_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1000) begin
				led_data <= _8_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1001) begin
				led_data <= _9_;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1010) begin
				led_data <= A;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1011) begin
				led_data <= B;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1100) begin
				led_data <= C;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1101) begin
				led_data <= D;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1110) begin
				led_data <= E;
				zeroflag = 1;
				
			end
			else if (read_data[7:4] == 4'b1111) begin
				led_data <= F;
				zeroflag = 1;
				
			end
			else begin
			end
		end
			$display ("led_data = %b", led_data);
		end
	//end
	
		always @(posedge clk_50MHz, negedge reset_b)
		begin
		//if (read_data) begin
	   if (reset_b == 1'b0) begin
         led_data2 <= _0_;
      end
		else if (read_data[3:0] == 4'b0000) begin
         led_data2 <= _0_;
			zeroflag2 = 1;
      end
      else if (read_data[3:0]== 4'b0001) begin
         led_data2 <= _1_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0]  == 4'b0010) begin
         led_data2 <= _2_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0]  == 4'b0011) begin
         led_data2 <= _3_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0]  == 4'b0100) begin
         led_data2 <= _4_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0]  == 4'b0101) begin
         led_data2 <= _5_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0]  == 4'b0110) begin
         led_data2 <= _6_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0] == 4'b0111) begin
         led_data2 <= _7_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0] == 4'b1000) begin
         led_data2 <= _8_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0] == 4'b1001) begin
         led_data2 <= _9_;
			zeroflag2 = 1;
      end
		else if (read_data[3:0] == 4'b1010) begin
         led_data2 <= A;
			zeroflag2 = 1;
      end
		else if (read_data[3:0] == 4'b1011) begin
         led_data2 <= B;
			zeroflag2 = 1;
      end
		else if (read_data[3:0] == 4'b1100) begin
         led_data2 <= C;
			zeroflag2 = 1;
      end
		else if (read_data[3:0]== 4'b1101) begin
         led_data2 <= D;
			zeroflag2 = 1;
		end
		else if (read_data[3:0] == 4'b1110) begin
         led_data2 <= E;
			zeroflag2 = 1;
      end
		else if (read_data[3:0] == 4'b1111)	begin
         led_data2 <= F;
			zeroflag2 = 1;
      end
		else begin
		//end
		end
		//$display ("led_data2 = %b", led_data2);
	end
      
		
	always @(posedge clk_xxMHz, negedge reset_b)begin


			$display ("delay_c = %d", delay_c);
			$display ("flag= %d", delay_flag);
		   
			if (reset_b == 1'b0) begin  			
				led_dis <= _0_;// change back to 0 after testing
				dis_control <= 4'b0011;
				delay_c <= 28'd0;
				delay_flag <= 0;       // flag to set how long to display for
			end
			
			else if (delay_c < 10/*change after test 50000*/ && (read_data))   begin
				delay_c <= delay_c +1;
				delay_flag <=0;
				
				if (counter == 0) begin    // counter to set which led on
						dis_control <= 4'b1110;
						led_dis <= led_data2; 
						counter <= counter + 1;					
				end
				else if (counter == 1) begin
						dis_control <= 4'b1101;
						led_dis <= led_data;
						counter <= counter + 1;
				end
				else if (counter == 2) begin
						dis_control <= 4'b1011;
						led_dis <= led_data3;
						counter <= counter + 1;
				end
				else if (counter == 3) begin
						dis_control <= 4'b0111;
						led_dis <= led_data4;
						counter <= 0;
				end
			end
			
			else begin 				//1 : begin
						delay_flag <= 1;
						delay_c <=0;
			end					
	end //  end always block
	
		//PED p1( .i_signal(delay_flag), .i_clk(clk_50MHz), .i_rst_b(reset_b), .o_pulse(data_displayed));
		PED p2( .i_signal(delay_flag), .i_clk(clk_50MHz), .i_rst_b(reset_b), .o_pulse(read_pulse));
  /**************************************************z*********
   * Module Instantiation                                    *
   ***********************************************************/
   slowclock
      my_clock (
         .clk       (clk_50MHz),        // I      50MHz
         .clk_xxMHz (clk_xxMHz)); // I      800Hz 

endmodule
